There are many types of applications (e.g., communications) for which it is desirable to process a high number of high speed signals on a single circuit. For example, components of communication infrastructure typically require the processing of transferred data at a performance capable of supporting the maximum defined data rate. Such data processing may include protocol dependent functionality such as synchronization, data detection, field extraction, field construction, data processing, data formatting, and hierarchical manipulation. Additionally in many cases the communication component interfaces between multiple channels connected to multiple infrastructures with similar or totally different conventions.
For example, many high speed communications signals such as Plesiochronous Digital Hierarchy (PDH) or Synchronous Optical Network (SONET) signals include a multiple sub-channels and data links. Such communication signals may include high priority system messages between various pieces of communication switching equipment, such as high-level datalink control (HDLC) formatted messages. Such signals may also include high priority messages known as BOM messages (bit oriented messages) which may contain a 1 byte abort signal and a 1 byte code message. DS3 or T3 signals typically include 28 DS1 or 28 T1 sub-channels, respectively, and therefore require the processing of 28 individual sub-channels. This presents the problem of how to process these multiple signals. The use of multiple ICs, each capable of processing a single channel may be impractical due to space, power consumption, and cost constraints.
Providing high-speed signal processing for multiple channels (or even for a single channel processing multiple protocols) can dramatically reduce the overall cost of such applications. Some advances have been made in this area. For example, communications equipment manufacturers have attempted to achieve higher density processing of communications signals. Higher density processing allows more high-speed communication signals to be processed on a circuit board or chip of a given cost than was previously possible.
In general, in designing an integrated solution, the various considerations that need to be addressed include the total bandwidth requirements, the number of channels to be concurrently supported, and the number and complexity of protocols supported. In addition, interoperability, scalability, and costs are also factors in the design process.
Conventional implementation of an integrated solution for multiple channel processing has severe disadvantages. Typically, an IC for multi-channel processing integrates multiple repeated instantiations of sub-components each handling one specific channel carrying one specific protocol. Additionally, each sub-component processes its data channel by sequentially processing data grains, either received or generated, one at a time. For conventional systems a data grain is typically a single bit, or a group of, at most, a few bits. Such an approach is inefficient for large scale multi-channel and multiple protocol, high bandwidth, applications. The inefficiency is due to the massive redundancy in logic and physical resources for each channel and for similar functions of the different protocols. Moreover, within a single channel carrying a specific protocol, independent data processing is performed sequentially. This results in a scalability barrier making typical solutions impractical for applications requiring multi-channel, multiple protocol, high bandwidth data processing.